1. Field of the Invention
The present invention relates to a method of routing and sizing of wires in the formation of wiring paths extending through a region; and more particularly, relates to optimizing the routing and sizing of printed wire circuitry on a single surface, such as on semiconductor devices.
In the implementation of the positioning and sizing of the printed wire circuitry on semiconductor devices or substrates, an important aspect is to be able to utilize printed wire widths and spacings which are optimized with regard to the amount of available spacing on the surface of the device or substrate. In particular, for fine pitch ballgrid array chip carriers (PBGA) the printed circuitry wire widths and spacings vary in accordance with the amount of space which is available on the device or semiconductor surface. Thus, as the available spacing for the printed wires decreases, in view of the number of wires which must pass between the ballgrid array paths or other converting locations or the like, the width of each respective wire must necessarily decrease; whereas conversely, as the available space increases, the wire widths should also be increased in order to take advantage of the increased spatial availability.
Presently, optimization of printed wire circuitry through the intermediary of correlating wire widths and spacing in conformance with available surface space is implemented essentially manually, utilizing design automation of presently known software systems; for instance, such as AutoCad, Cadence, IGS or GYM. In order to be able to optimize the wire sizing and spacing of printed wire circuitry on a surface, such as that on a semiconductor device or the like, a single surface layer may potentially require as much as eighty hours of experimentation and implementation by a designer in order to obtain an optimized wire sizing and spacing on the surface.
2. Discussion of the Prior Art
Although numerous publications are currently available which direct themselves to the routing and spacing of printed wires on surfaces, for instance, such as on single surface or multiple surfaces of semiconductor devices, these do not address themselves to the problem of obtaining optimized printed wire widths and spacings in correlation with the amount of available spacing across a particular surfaces onto which the wires are to be applied.
Rostoker et al. U.S. Pat. No. 5,808,330 and associated Scepanovic U.S. Pat. No. 5,578,840 each disclose multi-directional interconnect routing of wiring and orthogonal through-connect for the terminals of microelectronic cells of integrated circuits. In particular, the routing architecture discloses hexagonally shaped cells, although other polygonal shapes such as triangles or parallelograms maybe utilized in order to provide for a tri-directional or multi-directional routing of wiring across surfaces. There is no disclosure or suggestion of optimizing wire widths and wire spacing over available surface space so as to optimize the printed wire circuitry on an essentially single surface of a semiconductor device.
Hama et al. U.S. Pat. No. 5,808,969 discloses a method and apparatus for deciding a wire routing and for detecting a critical cut when positioning printed wire circuitry on a surface. There is no disclosure of optimizing wire size and spacing in correlation with an available surface area.
Chang U.S. Pat. No. 5,581,098 discloses circuit routing structure in a multi-layer product and does not address itself to the optimization of interconnect wire widths and spacings or positioning thereof on an available surface area.
Koike U.S. Pat. No. 5,473,195 relates to a wiring arrangement which is variable in width or intervals when positioned on semi-conductor integrated circuit devices or chips. Wire widths are computed so that the propagation times for multi-bit signals arrive at the same time when different wire lengths are required for each bit. There is no suggestion of the optimization of wire widths and wire spacings in correlation with an available surface area on a semiconductor device.
Yip et al. U.S. Pat. No. 5,465,217 pertains to the provision of fan out patterns for wire routing in order to attain allowable combinations of fan in and fan out angles, so as to select optimal routing on the basis of electrical characteristics. There is no utilization of optimizing wire widths and spacing with regard to correlation with a semi-conductor or ballgrid array surface area.
Kappel U.S. Pat. No. 5,400,063 relates to the wiring layout for ink jet printers and, resultingly provides for optimizing wire widths and spacing in a limited manner directed to special applications which do not lend themselves to a routing of optimized wire widths and spacings at any angle across an available surface area.
Shikata et al. U.S. Pat. No. 5,309,371 relates to the layout of positions of integrated circuit blocks on a semiconductor chip, generally referred to in the technology, as floor planning. The publication does not address itself to the optimization of wire widths and spacing in correlation with an available surface area on which the wire circuitry is being plotted.
Chang et al. U.S. Pat. No. 5,295,082 relates to the orthogonal wiring of multichip module interconnects and does not address itself to the optimization of wire widths and spacings when routed across an available surface area, such as the surface of a semiconductor device.
Cobb U.S. Pat. No. 5,187,671 pertains to selecting the shortest to the longest wire paths utilizing binary trees in order to provide for an automated interconnect routing system. There is no disclosure nor suggestion of employing optimization of wire widths and wire spacings correlated with available space on a semiconductor surface.
McGehee U.S. Pat. No. 4,852,016 relates to integrated circuit chip layouts and wiring, but does not address itself to optimization of wire widths and spacing in correlation with available surface areas on a semi-conductor device.
Fitzgerald et al. U.S. Pat. No. 4,746,966 is directed to integrated circuit chip layout and wiring with regard to logic circuit layouts for large scale integrated circuits. There is no disclosure of optimizing wire widths and spacings in correlation with available surface areas on a semiconductor device.
Hechtman et al. U.S. Pat. No. 4,642,890 is directed to a method for routing non-crossing conductive paths such as wires extending between each of two families of conductive nodes, and which may employ electrostatic analog aspects. There is no optimization of spacing between conductors nor is there any optimization of conductor wire width in correlation with an available surface area on a semiconductor device.
Finally, Isett U.S. Pat. No. 3,621,208 pertains to the arrangement of connections with regard to single point interconnection routing in accordance with wire lengths. There is no concern with regard to the optimization of wire widths and wire spacings in correlation with available surface space, particularly on an semi-conductor device.
In summation, none of the prior art publications or those known in the current technology address themselves to the routing of wiring paths through a surface region, particularly such as in a semiconductor device, and wherein there is provided an optimization of wire sizes and spacings in correlation with available surface areas on the device.
According to the invention, an optimized printed wire circuitry provided on a single surface through the adjustment of wire line widths and placement is, in effect, implemented through the intermediary of a computer software algorithm which automatically routes printed circuit wires while adjusting wire widths in a placement according to available space, so as to route the wiring paths between lands or other fixed shapes or patterns, such as BGA pads, by connecting the lands through the provision of a region having borders, and which are positioned at intersections of the borders and lands and from a box-like area therebetween. Provided are a plurality of guidelines, each of which intersects one or more of the borders or lands, by determining the number of guidelines intersecting each of the borders, positioning on the borders equal-diameter imaginary circles of the same number as the number of guidelines intersecting the borders, and stepping the circles inwardly in a software algorithm while adjusting the diameters of adjacent of the circles to fill the spaces between the lands thereby forming paths of circles, defining the routing and wire sizing of optimized wiring paths according to the paths of the inwardly stepping circles and diameters of the circles, respectively.
The foregoing; in essence, provides for an optimization through the application of a software or computerized algorithm using adjustable diameter circles in correlation with guidelines so as to be able to optimize the respective wire widths and their angular projections and mutual spacings in correlation with an available space or region within the borders having the lands connecting the corners thereof.
In essence, this will enable all the wires within a specified surface area to be routed, sized and spaced concurrently in time from the beginning to the end of the algorithm within a minimum period of time, thereby drastically reducing present time requirements in laying out optimized wire line widths and placement or surface routing conditions.
Accordingly, it is an object of the present invention to provide a method for the optimization in a computerized algorithmic mode of wire widths and spacings thereof for the formation of printed wire circuitry on a surface area in correlation with the space available thereon.
A further object is to provide a method of optimizing in a printed wiring circuit wire widths and spacings extending across a single surface area of a semiconductor device.
Yet another object of the present invention is to provide an algorithm utilizing computer-generated guide lines and stepped circles for rapidly and efficiently analyzing available space on a surface area so as to be able to route a plurality of optimized wire sizes and spacings in conformance with a surface area on a semiconductor device, such as BGA carriers, which is available for routing and positioning the wires.